Binary counter



April 27, 1965 Filed Jan. 24, 1961 7 Sheets-Sheet 1 ,24 FIGJ. A f

"1 :l jv 22 I i I 20 MAXIMUM r l I seven r 6 maws MAXIMUM SLOGIC A OR I 26 INPUTS l J {630 V I LTO I MAXIMUM A as 3 THREE IN'VERTED W OUTPUTS MAXIMUM 4 LOGIC ANDINPUTS F1613. FIG. 2.

I IO 34 NO l 2 a a I 2 a I; 1 r- LOGIC OR ug? INPUTS TIMES E1615. a INVENTOR FIG.5D F-|e.sc mass FIG.5A CHARLES ICASALE 11 ATTORNEYS April 1965 c. T. CASALE u 3,180,975

BINARY COUNTER Filed Jan. 24, 1961 7 Sheets-Sheet 2 OUTPUT REG. C

F1624. gg f PRIOR ART INP REGI ER i INVENTOR i- B.-- g

CHARLES T. CASALE 11 l SLAVE BY MwfiufMM ATTORNEY S April 27, 1965 c. r. CASALE n BINARY COUNTER 7 Sheets-Sheet 5 Filed Jan. 24, 1961 1L JL L 00 355 .o mofiw C. T. CASALE ll April 27-, 1965 BINARY COUNTER 7 Sheets-Sheet 4 Filegl Jan. 24, 1961 April27, 1965 c. T. CASALE ll BINARY COUNTER 7 Sheets$heet 5 Filed Jan. 24, 1961 C. T. CASALE ll BINARY COUNTER April 27, 1965 7 Sheets-Sheet 6 Filed Jan. 24, 1961 I/VVf/VIOR CHARLES 1: CASALE II E mwf ATTORNEYS April 27, 1965 c. T. CASALE n 3,

BINARY COUNTER Filed Jan. 2 1961 v Sheets-Sheet 7 STAGE OI STAG E 00 CHARLES 'r. CASALEII' W 9%VW ATTORNEYS United States 3,180,975 BINARY CGUNTER Charles T. Casale ll, Minneapolis, Minn, assignor to Sperry Rand Corporation, New York, N .Y., a corporation of Delaware Filed Jan. 24, 1961, Ser. No. 84,535 30 Claims. (Cl. 235--92) systems such as computers for the purpose of providing outputs which successively are different by plus or minus decimal one to indicate the next address for a stored program for example. Generally, a program address counter is updated by decimal one once each cycle to give the new address for the next program, though it may be down dated by decimal one or otherwise changed up or down to a given decimal number for purposes of obraining from the computer memory a given jump instruction. in the counter described in this application, provision is not herein made for changing the'contents of the counter by more than decimal one. However, viously, sucha provision may be added by those of ordinary skill in the art without departing from the scope of this invention.

The speed of changing the contents of a binary counter in computers and other equipment has become more and more important as other elements in computers or data processing systems have been made faster in operation. By the present invention, it is possible to change the contents of a binary counter by decimal one in two clock or phase times as compared with four phase times heretofore required and this without increasing the amount of equipment necessary in the counter. in other words, by using the same amount of hardware as i employed in existing bit counters for example, and using the same clock rate, a 15 bit counter can be constructed in accordance with this invention to count in one-half the time previously required.

It is therefore one of the main objects of this invention to decrease substantially the amount'of time required to change the count in a binary counter by decimal one.

Another object of this invention is the provision of a binary counter which has means for at least temporarily storing a plurality of binary signals representing a given binary number to be changed as in the previous object, along with means for combining certain of those binary signals into at least one signal representing a logical Nor function, plus means for combining certain of those binary signals into at least one signal representing a logical And function, and means for effectively combining all of the binary, Nor, and And signals into-a plurality of binary signals which represent the changed binary number.

Still other objects of this invention will become apparent to those of ordinary skill in the art by reference to the following detailed description of the exemplary embodiments of the apparatus and the appended claims. The various features of the exemplary embodiments according to the invention may be best understood with reference to the accompanying drawings, wherein:

FIGURE 1 illustrates circuitry representing a logical element useable in the present invention,

FIGURE 2 illustrates two series of nonover-l-apping phasing pulses,

FIGURE 3 is a shorthand symbol for a part of the circuitry illustrated in FIGURE 1,

" atet of this invention uses a plurality of logical elements of the type disclosed and claimed in the copending Cray application, Seiial No. 855,188, filed November 24, 1959. Such a logical element is illustrated in FIGURE 1 of the present application within the dash line ll Briefly, the circuitry operates such that when a pulse is delivered to Or circuit 12 via any one or more (i the input lines l i,

the Or circuit provides a pulse output to amplifier 16.

This amplifier inverts a pulse and applies the inverted pulse to amplifier 13, causing an output signal on each of the seven output lines 26 for the duration of the pulse. The output of amplifier 18 is also applied back to Or circuit 12 via And circuit 22 which is gated by a timing signal s5 If the original pulse via one or more of lines it was gated to Or circuit I12 by a timing pulse of phase (M with the and pulses being as indicated in FIGURE 2, the output from Or circuit 12 due to an input from And circuit 22 maintains a signal on lines 20 for a second phase time since there is inherently some delay in amplifiers l6 and 18, all as explained in the above-mentioned Cray application. When the timing pulse B ends, the output on lines 2d Will cease if there is no input to 0r circuit 12 at that time. Nevertheless, with one regenerative cycle by the first pulse, the logic input is at least temporarily stored. If it is desired to maintain a signal on lines 29 corresponding to the logic of the pulse or pulses applied at one or more of lines 14, for more than two phase times, the output of amplifier 18 may also be gated back to Or circuit'12 via And circuit 24 by timing pulses of phase 41 In other words, the internal feedback circuit including And circuit 22 will maintain the output for an additional phase time, and the external feedback circuit including And circuit 24 will maintain the output for still another phase time. As long as the tilting pulses and o are recurrent as indicated in FlGURE 2, any logic input will continue to be provided on lines 20 until one or the other of the timing pulses ceases to recur. I

For purposes of describing this invention and in order to aid in the realization of why certain connections are made, it may be assumed that Or circuit 12 has a maximum capacity of five logic Or inputs, that the number of normal or uncomplemented outputs as available from amplifier 18 is seven (one for each line 29), and that the maximum number of inverted or complemented (Not) outputs from amplifier 16 is three as indicated by the three lines 26. A further assumed limitation is that the sum of thenumber'of logical Or inputs, inverted outputs, and normal outputs must not exceed ten for any one logical element. Additionally, it may be assumed that the And circuits which are utilized in this invention may have a maximum. capability of four logic inputs, such as shown for And circuit 23. This maximum number of logic And inputs does not include the timing input 39.

It should be understood that the limitations set forth in the last above paragraph are exemplary, and that the invention herein is not necessarily limited thereby.

The logical element ltl of FIGURE 1 appear in the other figures of this application as a circular element as shown in FIGURE 3, with a dash line half moon and wa ers a plus sign indicating Or circuit 12 which receives the logic Or inputs. The phase of the internal timing pulses to And circuit 22 in FIGURE 1 is shown in FIGURE 3 merely by a phase designated arrow 31 to the perimeter of the circular element 10. As indicated in both FIG- URES 1 and 3, these pulses are of phase but as will become apparent, the internal phasing may be by pulses whenever the logic Or inputs are tinned by pulses. The external feedback circuit of FIGURE 1, which includes And circuit 24, is schematically illustrated in FIGURE 3 with dot 24 representing the And circuit. This dot type of And circuit representation is used hereinafter whenever timing pulses to an And circuit gates no more than just one input signal. Whenever two or more input signals are to be gated by a timing pulse, regardless of which phase it may be, the And circuit involved is shown in box form similar to And circuit 28 of FIG- URE l.

The inverted outputs from the logical element 10 in both FIGURES l and 3 are indicated by a small circle 32 intersecting the larger circle representing element 10. That is, circle 32 in FIGURE 3 indicates that any output signal on line 34 is an inversion, binary complement, or logical Not of the logic Or input. All normal output lines connect directly to the perimeter of circle 10 without any smaller circle 32 intervening.

Whenever more than one inverted outputs are taken from a logical element 16 at the same time, more than one output line is used for that purpose. In FIGURE 3, the number 3 within circle 33 indicates there are three output lines (as lines 26 in FIGURE 1) for carrying inverted outputs. Similarly, the number of output lines which simultaneously carry normal or uncomplemented outputs is designated by a circle with that number inside it. Whenever an output line of either type does not contain an encircled number, it may be assumed that there is only one conductor in that line unless obviously there are more.

As an example of a binary counter which may employ logical elements of the type shown in FIGURES 1 and 3, reference is made to FIGURE 4. It may be immediately noted that none of the large, circular, logical elements 10 in FIGURE 4 employs any external feedback. That is, the external timed And circuit 24 of FIGURES 1 and 3 is not utilized in FIGURE 4 with any of the logical elements. Use is made of the external feedback circuit how ever in later figures in this application.

The counter shown in FIGURE 4 has five binary stages 04, and any binary number permanently or temperarily stored in the input register A may be changed by decimal one in two phase times. That is, if the internal feedback of the logical elements in the input register is gated by the timing pulses, for example by e then the changed binary number is available for example in the output or sum register C during the next phase time c11 with only the phase time intervening.

In detail, the counter of FIGURE 4 operates to increment or update the binary number in the input register A by decimal one in the following manner. Generally, the normal outputs of the A register logical elements are applied respectively to the five stages of a slave register A. Each of the outputs from the A register is timed enroute to the slave register by pulses. Accordingly, the respective Or circuits in the slave register A receive the input register outputs during a (11 phase time, and the internal feedback of each of the slave register logical elements is timed by pulses.

Along with applying the outputs of the input register A to the slave register A, the A register outputs are also applied in certain combinations to a sensing register B. This register requires only four logical elements B B B and B As may be noted, the inputs to the respective Or circuits in the sensing register B are timed by 1);; pulses. The normal output on line 36 from element A is applied directly to the B sensing register element. However, the

B sensing register element receives the result of intervening And circuit 38 which has as logic inputs the normal outputs of both the input register elements A and A The input And circuit 40 for the element B of the sensing register provides an output only when the A A A normal outputs are all binary 1s. In a similar mannet the input And circuit 42 for the B sensing register element provides an input thereto only when the four lower stage input registers all contain a binary 1. Since the input to any logical element 10 of the B register is during phase B, the internal feedback path of each B register elements is timed by the pulses.

Since in incrementing a binary number by decimal one the least significant digit needs only to be inverted, the inverted output of slave register A is applied directly to the Or input circuit in the output element C with a 42 timing. For the other four stages, however, both inverted and normal outputs from the slave and sensing registers are employed and Anded to provided the necessary Or inputs to the respective C register elements. For example, the inverted output from slave element A' as it appears on line 44 is Anded in circuit 46 with the normal output as it appears on line 48, from the sensing element B In a similar manner, the normal output from element A on line 50 is Anded in circuit 52 with the inverted output on line 54 from the sensing element B Both And circuits 46 and 52 are timed by 41;, pulses, so that the inputs on their respective output lines 56 and 58 are applied to the Or circuit 60 in element C during phase A times. This means that the internal phasing of element C must be accomplished by pulses, as illustrated.

The normal and inverted outputs of the other slave and sense register elements for a given stage are combined in a similar manner to provide the Or inputs for their associated output register C element. That is, the inverted output of A and the normal output of B are applied to element C via And circuit 62, while the normal output of A' and the inverted output of B are applied thereto via And circuit 64. And circuit 66 receives the inverted output from A' along with the normal output from 13 while circuit 63 Ands the normal output from A with the inverted output from B In like manner, And circuit 70 receives the inverted output from A' along with the normal output from B while And circuit 72 does the reverse thereof.

As above indicated, with the circuit of FIGURE 5, a binary number, for example 0011-1 (least significant digit on the right) is incremented by decimal one with the resultant (01000, in keeping with the example) being available in the output register C in two phase times. It should be understood that in FIGURE 4, as well as in the counter circuits later herein described, that the outputs of the And circuits 74, 46, 52, 62, 64, 66, 68, 70, and 72 may be applied back into the respective stage Or circuits of the input register A, this being the preferable mode of operation for the FIGURE 4 circuitry. In other words, the output register C is actually preferably register A, and not a separate register.

With the circuit of FIGURE 4, it becomes apparent upon analyzing the progression of the number of inputs to successive And circuits which feed the sensing register, for example And circuits 38, 40 and 42, that for each additional stage in the counter, additional logic input must be available in the And circuit. Since one of the limitations above mentioned for the And circuits for this invention is that they have a maximum capacity of four logic inputs, it is apparent that a counter logically arranged as in FIGURE 4 can have no more than five stages since addition of a sixth stage would require that the associated And circuit providing the input to the sixth stage sensing element would need to have five logical inputs. For N stages in a counter of the FIGURE 4 type the maximum number of logic inputs to the last stage And circuit may generally be expressed as (N1). When N is greater than five, this quantity is too great. In

the past, this problem has been obviated by a fanning out type arrangement, providing a counter of more than five stages with no And circuit having more than four logic inputs. However, such a counter requires four phase times for incrementation. According to the pres ent invention, however, incrementation by decimal one of a more-than-five-digit binary number can be effected in two phase times without any And circuit having more than four logic inputs and without increasing the amount of required equipment. In general, the maximum number of logic inputs to any And circuit in a counter built in accordance with this invention is (N-P) where N is the number of stages and P is an integer greater than one but less than N.

A counter constructed in accordance with this invention with the quantity (N-P) equal to four and the number of stages N equal to fifteen is illustrated in FIGURES 5A, 5B, 5C, and 5D which may together be thought of as FIGURE 5 since they go together as shown in EEG- URE 5 to make up the whole counter.

In FIGURE 5, the input register, i.e., the register which at least temporarily stores the binary number to' be incremented, includes each of the 15 logical elements A A In this specific embodiment, the input register also includes logical elements A A for purposes which will hereinafter become more'apparent. One logical Or input of each of these elements in the input register is utilized to receive the respective binary signal representing thebinary digit (bit) of the associated stage. These binary signals are originally applied to the respective stage input lines lltitl of which there is one for each stage, and are gated to the input register logical elements A and A by timing pulses. The internal phasing of each of the input register elements A and A is by pulses.

' Besides the duplication of the temporarily stored signal in each of the A elements by each of the A elements, there is also included in the counter of FIGURE a slave register comprising logical elements A A' which effectively store the same signal as on the associated stage input line 1% since in each instance it Will be noted that the input to the internal Or circuit of each A element is the normal output of the respective A element of the input register. Each of the A element inputs are timed with 3 pulses, and the internal feedback timing for the A elements is by pulses. In addition, each of the A slave register elements is illustrated as having an external feedback path which is timed by pulses. As above explained, this external feedback operates in conjunction with the internal feedback to store the signal in the elements for as long as both the 3 and pulses continue to recur. As soon as one or the other of these strings of pulses is stopped, storage of the instant signal in an A element ceases. It is to be understood that the external feedback path for each of the slave register A elements is not essential for this invention, but may be employed if desired for whatever advantage such may have in using the counter with other equipment. If the external feedback paths are employed, it is desirable at times to clear or destroy the instantly stored information in each of the A elements, as at the beginning or before an incrementation of the contents in the input register is started. This can be conveniently done by stopping the 5 pulse series temporarily,.for example by inhibiting one of the 4; pulses, by means not shown.

Also included in the counter of FIGURE 5 is a sensing register which includes 15 logical elements B B Any input to the internal Or circuit of each of these B elements iselfectively timed by a pulse, and the internal feedback paths of the 13 elements are timed by pulses. The signal stored in some of these B elements is eifectively a duplicate of the signal originally on the associated line 106'. For example, it may be noted that the B element receives in its Or circuit only the normal output of the A element. Consequently, the normal output of B is the same as the normal output of A which in turn is the same as the input signal on line let} to the A element. However, the signal stored by other B elements is not necessarily the same as stored by its associated A element. For example, the B element has 3 inputs to its Or circuit which are respectively inverted outputs of the A A A input register elements. As a further example, the input to the Or circuit of sensing element B is from And circuit 162 which in turn receives three inputs which are respectively the normal outputs of elements A 0, A0 and A plus a timing signal of phase B. In both of these examples, it is apparent that the signal stored by the B and B sensing elements is not efiectively a duplicate of the respective signals stored in the A and A As a matter of fact,

the signal stored in the B element may be logically expressed as a Nor signal since it is the result of Oring the inverted or logical Not signals from the A 'A and A elements. In a similar manner, the signal stored in the B sensing element is the result of Anding the normal outputs of the A00, A01, and A input register elements. Consequently, the normal outputs of the B and B sensing elements may be considered as Nor and And signals respectively. On the other hand, if element B had an inverted output (which it does not, but which element B for example does and likewise receives in its internal Or circuit several different Not signals) the inverted output of B can be considered a Nor-Not signal. Similarly, the inverted output on line 164 of sensing element B maybe considered an And-Not signal.

a As illustrated in FIGURE 5, the binary counter may also include a separate output register including logical elements C C The input or inputs to the re spective 0r circuits in each of these logical elements is from a respective one or more And circuits. The combination of the AND circuits providing OR inputs to the logical elements C C can be considered for the purposes of this. specification and the claims as ANDING-OR means. In FIGURE 5A, these And circuits are represented by a rectangular box with an ampersand sign (8:) insideit. In addition, each of these And circuits is designated by a number preceding the letter C. Where the number of And circuits in a particular stage is greater than one, the'left hand And circuit is designated 1C, with the next And circuit to the right in the same stage being designated 2C, etc. In order to simplify the illustrations, the similarly disposed And circuits in FIGURES 5B, 5C, 5D do not contain the ampersand sign, but instead contain the 1C, 2C, etc. designation. Whenever an output from an A or B logical element serves as an input to one of these And circuits and the output line is not drawn directly to that And circuit but has a designation associated therewith, the first number in the designation indicates the stage number, while the latter part of the designation (that after the hyphen) indicates to which of the C designated .And input circuits that particular output goes. For example, one of theoutputs sensing B is designated 7-40. On looking at FIGURE 5C which contains stage @7 of the counter, it Will be noted that the And circuit designated 4C in stage 7 has an input from element B Similar designations are made in other parts of FIGURE 5.

The combination of the AND circuits providing OR in puts to the logical elements C C can be considered for the purposes of this specification and the claims as ANDlNG-OR means.v

In prior art binary counters, the circuitryfirst determines what bits of the stored binary number need to be changed to increment that binary number by decimal one and then proceeds to change those bits. The counter of FTGURE 5 (as well as that of FIGURE 4) utilizes not only the conditions for change, but also the conditions for not changing bit values. The entire sets of these two conditions are, for any given counter of base 2,

mutually exclusive and totally inclusive for a total of 2 unique values. If there exists then a listing of the Z values that a counter may assume, the counting function can be implemented by looking at the value, determining where it lies in the list, and selecting the next value on the list. Counting then becomes a matter of table look-up. On considering this on a bit basis, it can be seen that any given bit can be described as the kth bit in a counter, so that all bits of value 2 and greater can be ignored in in determining the value of the bit 2 For any bit, then, it is apparent that it will be a binary 1 after the whole binary word has been incremented by decimal one under the following conditions: (1) that bit was a O and all lower order bits were both 1, (2) that bit was a 1 and any one of the lower order bits was 0.

Since there is no concern about the bits higher than the particular stage of interest, the generalized logical expression for the kth stage is as follows:

wherein any A and its binary logical Not equivalent K with their respective stage subscripts effectively refer to that stages binary signal of the binary number stored in the input register elements A or A", or in the slave register elements A' or any combination of these. In FIG- URE 5, the number of input And circuits to any one of the output elements C is limited to a maximum of four in keeping with the limitation that the maximum number of Or inputs to any one logical element is five, one of the Or inputs being reserved to load the element initially. In other words, this refers to what was above indicated relative to FIGURE 4, that the output register C can be, and preferably in accordance with this invention is, the same register as the input register as it consists of elements A A This means that in the preferred embodiment, the A and C elements for example are one and the same element instead of being different elements as indicated in FIGURE 5. With the limitation that the maximum number of And circuits which provide respective inputs to the single Or circuit within a C element being four, the maximum logical expression for any stage of the counter in FIGURE is in the form of:

In this latter equation, X is the equivalent of one or more of the Anded A etc. terms in the other above equation, Y is one or more of others of those terms, and Z is the combination of the remainder of those terms. Y, Y, and Z are related respectively to the X, Y, and Z signals in accordance with one of the following:

( 1) Logical Not of same signal, (2) Logical Not of duplicate signal, and (3) De Morgan equivalent.

The De Morgan equivalent just referred to has reference to the two Boolean identities generally known as De Morgans Theorem, or Law, which says:

XY=X+Y Equivalencies of the De Morgan type are employed liberally in constructing the counter shown in FIGURE 5, and examples thereof are pointed out hereinbelow.

With the above information, and in view of FIGURE 5A, it is apparent that generally, updatingby demical one involves only the inverted of the signal stored by element A In the particular stage 60 equipment illustrated, this is accomplished by storing in slave element A' the normal of the signal in the A input element, and applying to the 1C And circuit in this stage the complement of the signal stored in element A This means that in equation form,

I 0o= '0u Of course, broadly speaking,

oo= n0 since 'oo= oo and 'oo= oo For stage 01,

01= 'o1( o0) 'o1( 0o) In effect, the last above equation says:

o1= o1( 0o) 01 oo) since B is the same signal as A and E is etfectively a duplicate of the K signal.

Before proceeding further with the C register output equations, the logical expressions which exactly reflect the outputs obtainable from the dilferent B elements in the sensing register, and which are utilized in the C equatlons, are now set forth:

From the foregoing equations for the respective sensing register output elements, several things may be noted among which is, as above indicated, the B normal output (without a bar over the letter) is a Nor signal as is the B signal, while E is a Nor-Not signal since it represents the inversion or complement of several Not signals which have been Ored. Further, as previously indicated, the normal output of element B is an And signal, while the inverted or complemented output therefrom as represented in the above equations by E is the binary logical Not of the B signal; in other words, an And-Not signal. It may also be noted that only the B B B B and B logical elements receive an And circuit output as their respective Or inputs. That is, as previously indicated, element Bog has And circuit 102 preceding it. For element B the output of And circuit 106 is its Or circuit input, while the outputs of And circuits 108, 110, and

112 respectively feed the internal Or circuits in sensing elements B ,B and B These sensing elements which are preceded by an And circuit receive only a single logic signal to their respective internal Or circuits, while the remainder of the sensing elements, except B B and B receive a plurality of logic inputs to their respective internal Or circuits. 7 Accordingly, the normal outputs from sensing elements B B B B and B are effectively Anded signals, while the inverted or complemented outputs therefrom are And-Not signals.

With the foregoing sensing register output signals in mind, and remembering that the outputs of the different slave register elements A may be complemented or noncomplemented so as to be representable respectively by an X or A, the following equations represent stage-by-stage the contents of the output register C after an incrementation by decimal one has occurred:

These C register equations can be correlated to the previously mentioned maximum logical expression C as it involves X, Y, and Z, and the logical Nots thereof. For example, relative to the equation for C it is apparentthat A' refers to X in the prior equation, with if being represented by 1' Y by A' and T by K' Since C0 involves stage 02, there are only two previous stages in the counter; therefore the equation for C does not involve any Z or 2 term. It should be apparent that these terms are also not involved in some of the other output equations, and that even some of the equations do not require a-Y or term, for example the equation for C03.

The C equation is of interest since the X and 3 1 terms are not direct inversions of each other, i.e., B is not the direct complement of B they are not normal and complement outputs from the same sensing element However, upon referring back to the equations for B and B it will be noted that the X, Y and Z terms are Anded to effect the B signal, while the respective logical Not of each of the same X, Y, and Z signals (K K K are Ored to effect the B signal. To prove that B =I one need only set down the Boolean identity of the B expression in accordance with the second De Morgan law above given, i.e.,

A similar type of situation exists for the resultant C and'C signals. g

To form the above C equation De Morgans theorem is employed. Since the generalized logicalexpression for C above indicates that the right hand term in parenthesis includes; i

os-lurios and there is no B sensing element which provides this resultant directly, equivalency therebetween and one of it) 7 the available outputs of the sensing elements is sought. Since in accordance with the second De Morgan law above set forth,

the 3, signal may be employed as the I? term of the equation for C The B and E terms are actually related to one another by one being the logical Not of the other, but the Y and Y terms (B and B are related to each other as De Morgan equivalents as above explained.

To the effect that the X term in the maximum generalized expression previously given need not be a normal or non-comp1emented signal, but that the X term instead is, reference is made to the C equation. 'In that equatiomX, Y, and Z are respectively Nor-Not signals F E and Ii while the Y, Y, Z signals are respectively just plain Nor signals B B and B the X and X terms of the C equation are related to one another such that one is the logical Not of the other. in this instance, the i signal is the logical Not of the same signal which constitutes the B signal, though it could be a logical Not of a duplicate signal; which is to say that the B signal itself may as well be made up of K or K signals instead of K signals, while the E signal remains as expressed in the equation therefor above.

Since this invention is not restricted to the arbitrary limitations referred to above in relation to the number of inputs and outputs for the logical elements and associated And circuits, broadly the equations for the output C register may be in accordance with the following logical expressions: oo=Eoo o1=e1( oo) 01 oo) 02= 02( o1 0s) 'lozc oi) 02( e0) os goa 02) 03 01) o4=04( oa 02-) +A04(ZO3)+AG4(B01) 05= 05 o t ss oz) O5( 4) 05 03) 'io5( o1) os= oe( as o2)+ os( o5)+ e s( o1) o7=Eov(os o5 o2) o'd os)+ o7( o5)+ o1 oi) ss= 0s( o7 o2) os( 07)+ oa( 01) oF od ss m ofi-ios oe) 09 07) c9( o2) 1O 10( 09 11 04)'i 10( 09)+ 10 11)+ 10( 04) ii u( ic 11 o4)'+ i1( 1u)+ 11( i1)+ 11( Q4) C12=Z12(B09E11F04)+AI2(FOB)+1412(B1t) 12( tn) 1s= 1s( 1a 11 0s) 13 13) 13 11) l 13 ot) 14 14( 14 11 04)+ 1( 14)+ l4( 11)+ 14( 04) wherein the difierent B and B signals are each as previously set forth in their respective logical expressions except that the following signals may be different:

EO9=A11A10A09 os= 11 10 o9 1o=f1o o9 1o= 1o o9 In other Words, broadly speaking, in accordance with the latter set of C output equations and B sensing'reg'ister equations, it is apparent that this invention does not require an A slave register at all, nor any of theinput signal duplicating logical elements A, as long as the itself assoon as two clock or phase times have expired.

To illustrate this clearly, FIGURE 6 is included as representative of the first two stages of the 15estage counter of 7 FIGURE 5 modified. In FIGURE 6, it will be noted that the output of And circuit EC in stage till is applied via line 114 back to the internal 0r circuit of logical element In any event,

A Since this And circuit is timed with a pulse, the incremented signal in A is available therefrom on the next pulse. In FIGURE 6, the incremented output of A is applied during a (1: time to the input of any utilization means, for example as to another logical element C' Similarly, the outputs of And circuits 1C and 2C in stage til are applied back to the Or circuit within the input register element A and the incremented bit therein is applied to the utilization element C The remainder of FIGURE 6 is similar to the corresponding stages in FIGURE with the exception that no A and A elements are shown in FIGURE 6.

In operation, as previously indicated, decimal one incrementation of the binary number, which is at least temporarily stored in the input register A, is accomplished in just two phase times. This does not include the phase time which may be required to load the input register initially. That is, with reference to FIGURE 6, the phase time represented by during which logic signals are applied to the A elements, is not counted. Starting with the A register filled with the binary number to be incremented, it is apparent that during the phase time 5 not only is the contents of the A register applied to the slave register elements, but also, and in parallel therewith during this same time, to the sensing register elements via And circuits where required, for example And circuit 192 in FIGU; E 5A, so that the output signals from the slave and sensing register elements are available by the end of the gu time. During the second phase time qb g, the contents of the slave and sensing register elements are maintained available and gated through their respective And circuits by a P timing pulse back into the associated A register elements, making the incremented binary numer available therein immediately so that it is possible to gate out that number into the respective C elements during the third phase time From the foregoing, it is then apparent that all of the A and B signals are formed during a first phase time and all of the resultant C signals for the respective C output register elements in FIGURE 5, or for the input back into the internal Or circuits of the respective input register elements A, are formed during the immediately following second phase time (A2).

As previously indicated, the second Or A logic ele ments in the input register are not required as long as the A elements therein can provide sufficient normal and inverted outputs. With the limitation above set forth as to the total number of logic Or inputs, normal inputs and inverted inputs not exceeding 10, it becomes apparent that some of the A elements are required when the C register per se is not used but the And circuit outputs are applied back into the associated A elements. For example, assuming that the A element in FIGURE 53 has a third normal output which would be applied to a C element as in FIGURE 6, and the S-IC, 5-2C, 53C, 5-4C And circuit outputs are applied to the Or circuit inputs within element A the total number of normal outputs, inverted outputs, and Or inputs to element A is 10. Since there is also required from stage 05 another inverted output, such as is indicated from the A element, this latter element is employed. A like situation exists relative to the A and A elements. The remainder of the A elements need not be employed at all even to stay within the limitation of a maximum of 10 for the total number of normal outputs, inverted outputs, and Or inputs.

Thus it is apparent that this invention successfully achieves the various objects and advantages herein set forth.

Modifications of this invention not described herein will become apparent to those of ordinary skill in the art after reading this disclosure. Therefore, it is intended that the matter contained in the foregoing description and the accompanying drawings be interpreted as illustrative and not limitative, the scope of the invention being defined in the appended claims.

What is claimed is:

1. A binary counter comprising means for at least temporarily storing a plurality of binary signals representing a binary number, means for combining certain of said signals into at least one signal representing a logical Nor function of the so-combined signals, means for combining certain of said binary signals into at least one signal representing a logical And function of the so-combined signals, and means for effectively combining all of said signals into a plurality. of binary signals representative of said binary number changed in value by decimal one.

2. A binary counter comprising means for at least temporarily storing a plurality of binary signals representative of a binary number, a plurality of means for respectively combining different groups of said binary signals into at least one logical Nor signal for each such group, a plurality of means for respectively combining diiferent groups of said binary signals into at least one logical And signal for each such group, and a plurality of means for eilectively combining all of said signals into a like plurality of binary signals representative of said binary number changed in value by decimal one.

3. A counter as in claim 2 wherein each of the last mentioned means includes And and Or means.

4. A binary counter comprising means for at least temporarily storing a pluraiity of binary signals representative of a binary number, a plurality of means for respectively combining different groups of said binary signals into at least one respective logical Nor signal for each such group during a first phase time and holding said Nor signals over into a second phase time, a plurality of means for respectively combining different groups of said binary signals into at least one logical And signal for each such group also during said first phase time and holding said And signals over into said second phase time, and a plurality of means operative during said second phase time to effectively combine certain forms of all said signals into a plurality of binary signals representative of said binary number changed in value by decimal one.

5. A binary counter comprising means for at least temporarily storing a plurality of binary signals representative of a binary number, means for inverting each of said binary signals to form logical Not signals, a plurality of means for respectively combining different groups of said Not signals in a logical Or sense to form at least one logical Nor signal for each such group, a plurality of means for respectively combining different groups of said binary signals into at least one logical And signal for each such group, and a plurality of means for effectively combining certain forms of all said binary, Not, Nor, and And signals into a plurality of binary signals representative of said binary number changed in value by decimal one.

6. A binary counter comprising means for at least temporarily storing a plurality of binary signals representative of a binary number, means operative during a first phase time for inverting each of said binary signals to form logical Not signals, a plurality of means for respectively combining different groups of said Not signals in a logical Or sense to form at least one logical Nor signal for each such group during said first phase time and holding said Nor signals over into a second phase time which immediately succeeds said first phase time, a plurality of means for respectively combining different groups of said binary signals into at least one respective logical And signal for each such group also during said first phase time and holding said And signals over into said second phase time, and a plurality of means operative during said second phase time for effectively combining certain forms of all said binary, Not, Nor, and And signals into a plurality of binary signals representative of said binary number changed in value by decimal one.

7. A binary counter comprising means for at least emporarily storing a plurality of binary signals representative of a binary number, means operative during a first phase time to invert each of said binary signals to form logical Not signals, a plurality of means for respectively combining dir rerent groups of said Not signals in a logical Or sense to form at least one logical Nor signal for each such group during said first phase time and holding said N or signals over into a second phase time which immediately succeeds said first phase time, a plurality of of for respectively combining different groups of said binary signals into at least one logical And signal for each such group also during said first phase time and holding said And signals over into said second phase time, means for inverting certain of said Nor and And signals to form at least one Nor-Not signal and at least one And-Not signal of each so inverted signal respectively, and a plurality of means operative during said second phase time to effectively combine said binary, Not, And, Nor-Not, and And-Not signals into a plurality of binary signals representative of said binary number changed in value by decimal one.

or= m( ss5os o2) 07 06) 07 05) 07 01 7 B =A A A =one or" said And signals,

8. A binary counter comprising means for at least temporarily storing a plurality of binary signals representative of a binarynumber, means for inverting each of said binary signals to form logical Not signals, a plurality of, means for respectively combining different groups of said Not signals in a logical Or sense to form at least one logical Nor signal for each such group, a plurality of means for respectively combining different groups of said binary signals into at least one logical And signal for each such group, means for, inverting certain of said Nor and And signals to form at least one Nor-Not signaland at least one And-Not signal of each so inverted signal re- 0 spectively, and a plurality of means for eiiectively combining said binary, Not, Nor, And, Nor-Not, and And- Not signals into a plurality of binary signals representative of said binary number changed in value by decimal one.

9. A counter as in claim 8 wherein each of the last mentioned means is in a different stage of the counter and provides for its respective krh stage a binary signal C of the said changed binary number with any C having a generalized logical expression of:

wherein any A and K with their respective stage subscripts eilectively refer respectively to that stages binary signal of the said stored binary number and the respective one of said Not signals, each of the said last mentioned means including its own predetermined number of And circuits up to a maximum of four with the maximum logical expression for any stage of said-counter being in the form of:

k k( k( k( k( wherein each of the X, Y, Y, Y, Z, and 'Z' signals eiiectivel'y refers to one of the said stored-binary, Not, Nor, And, Not-Nor, and Not-And signals with any X, Y, Z signal and respective X, Y, 2 signal being related to each other in accordance with one of the following:

(1) logical Not of same signal, (2) logical Not of duplicate signal, an (3) De Morgan equivalent.

it); A counter as in claim 9 having at least fifteen stages dtl 14 with the changed number binary signals for the respective stages being effectively in accordance with the following logical expressions:

'F ,=A Z A =one of said And-Not signals,

B =Z +Z +Z +2T +Z =one of said Nor signals,

E 7 Z 7+Z +Z 5+Z 4-|-Z@3 0I1e 0f Said NOTNOt B09 A11A1 A0g 0l'l Of said And signals, 7 73 =m=one of said And-Not signals, B =A A =one of said And signals,

F =m=one of said And-Not signals, B =2 },-1-Z +Z +Z +K =one of said Nor signals, ISII=ZO-B+EQ7-I ZOB+ZOE 4%;

' one of said Nor-Notsignals, B =A A A A =one of said And signals, F =Em=one of said And-Not signals, 14= 1s+ 12+ 11 10 09 one of said Nor signals, and

I one ofsaid Nor-Not signals.

11. A counter as in claim 10 including means for causing all the said B and T; signals to be formed during a first phase time and for causing all the said C signals to be formed during an immediately following second phase time.

12. A counter as in claim 9 including means for duplicating each of the said stored binary signals A to form at least one respective duplicate binary signal A for each counter stage and for inverting the A signal of each stage to form therefor at least one respective Not signal K which is a duplicate of a respective one of the afore mentioned Not signals K with the A and K signals being those actually stored in said storing means, there being at least fifteen stages (it) E4 in said counter with the changed number binary signals for the respective stages being effectively in accordance With the following logical expressions:

amass-s wherein:

Bm=Zog+Zm+Zoo=H of said NOI' signals, B =A A A =one of said And signals, F =m=one of said And-Not Signals, B =Z +Z +Z +Z =one of said Nor signals,

F =Z +Z +Z +Z =one of said Nor-Not signals, B =A A A =one of said And signals, FQJZZEABZZBEI one of said And-Not signals, B =Z +Z +Z +Z +K =one of said Nor signals,

F =ZE+Z+Zg+ZE+Z=one of said Nor-Not signals, B =A A A =one of said And signals, F =m= one of said And-Not signals, B =A A =one of said And signals, F =m=one of said And-Not signals, F =Z +Z +Z +Z +Z =0ne Of said N01 signals,

F11=ZQ3+ZG7+ZO5+ZO5+ZQ4=OH Of said Nor-Not signals, F =A A A A =0ne of said And signals, F =m=one of said And-Not signals, B =Z +Z +Z +Z +Z =one of said Nor signals,

and

F =Z +Z +Z +Z +Z =one of said Nor-Not signals.

13. A counter as in claim 12 including means for causing all the said A, K, B, E signals to be formed during a first phase time and for causing all the said C signals to be formed during an immediately following second phase time.

14. A counter as in claim 12 including means for effectively duplicating the A00 K A03 K A09 and X signals to form B 00, Boa, E03, B and E signals, respectively, to cause the said C C and C expressions to be:

storing means for at least temporarily storing binary signals A and A which are respective duplicates of the aforementioned stored binary signals A and A to cause at least the said logical expressions for B T5 B B respectively, to become at least:

16. A counter as in claim 12 including means in said storing means for at least temporarily storing a duplicate binary signal of at least the aforementioned stored binary signal A so as to give rise to the duplicate binary signal A means for inverting the A signal to form a 1ogical Not signal A means for duplicating the said B and B signals to form B and E signals in accordance with at least the following expressions respectively:

BIZZZOB 07+ os+ 05+Z04 12= os+ o7 +Z06+Z o5 o4 and including means for causing at least one of the C C C C C signals to be formed by using said B and F signals instead of said B and E signals respectively.

17. A counter as in claim 12 including means in said storing means for at least temporarily storing binary signals A A and A which are respective duplicates of the aforementioned stored binary signals A A A to cause the said logical expressions for B 15 9, B and B respectively to become at least:

oo= i1 1o os o9= 11 1o 09 O 1o= 1o o9 1o= 10 o9 means for inverting the A signal to form a logical Not signal A means for duplicating the said B and E signals to form B and B signals in accordance with at least the following expressions respectively:

12= oa+ o7+ os+ os+ c4 12= os+ o7|- 06+ (is-F M and including means for causing at least one of the C C C C C signals to be formed by using said B and B signals instead of said B and E signals respectively.

18. A counter as in claim 17 including further means in said storing means for at least temporarily storing binary signals A000, A001, A002, A003, A004, A006, A007, A A which are respective duplicates of the aforementioned stored binary signals A 4, A A and A means for inverting the A A A [1 signals to form logical Not signals 11 in, ez, 03 04 K006: 07 es 111621115 for p cating the said B B B and B signals to form respective E E B and F signals in accordance with the following expressions:

means for causing the said B and E signal expressions to become respectively:

09 11 1 u nn= 11 10 09 and means for causing the C C and C signal expressions to become respectively:

19. A counter as in claim 18 including means for causing all of the said A, K, B, 13 signals to be formed during a first phase time and for causing all the said C signals to be formed during an immediately following second phase time.

20. A binary counter comprising means for providing signals representing normal and complemented binary digits of a binary number, a plurality of means each for combining the signals for different groups of said complemented digit signals in a logical Or sense, a plurality of means each for combining the signals in different groups of said normal digit signals in a logical And sense, and a plurality of means, each including a different And and Or means, coupled to eifectively receive said normal and complemented digit signals and signals from each of said combining means for producing signals representative of said binary number changed in value by decimal one.

21. A binary counter comprising means including a first register having a plurality of stages for at least initially containing signals representing a binary number, a slave register, a sensing register, means for transferring said signals to said slave register during a first phase time and simultaneously filling the sensing register with Signals presenting a predetermined combination of normal and inverted digits of said number, said last mentioned means including a plurality of, And circuits each of which receives a number of said digit signals which is less by at least two than the number of stages in said first register, and a plurality of second And circuits coupled to the outputs of said slave and sensing registers for producing during a second phase time signals representative of said number changed in value by decimal one.

22. A binary counter comprising means including a first register having a plurality of stages for providing signals logically representing normal and complemented binary digits of a binary number at least temporarily representative of said binary number changed in value by decimal one. i

23. A binary counter comprising a register having a plurality of stages for containing signals representing in binary form the equivalent of a given decimal number;

and means for changing that number by decimal one in two phase times comprising: a plurality of And circuits divided into groups respectively associated with said stages with all said groups except that associated with the first register stage having more than one of said And circuits, means for providing during a first phase time normal and inverted signal versions of signals in said register, a plurality of Or circuits respectively associated with said groups of And circuits with an output of each And circuit being coupled 'to an input of its associated Or circuit, and means for applying said normal and inverted signal versions as logical inputs simultaneously to and conditionally through said And circuits to said Or circuits during a second phase time to cause from the Dr circuits a binary signal representation of a second decimal number which is different by decimal one than said given decimal number.

[24. A counter as in claim 23 wherein the last mentioned means includes a sensing register having a plurality of stages some of which receive a plurality of said inverted signal versions and combine them in a logical Or sense and others of which include means for receiving said normal signal versions and combining'them in an And sense witheach stage of said sensing register applytug to at least one of said And circuits as part of said logical inputs a normal signal versions of its logical contents while some of said sensing register stages apply to at least one other And circuit as another of said logical inputs an inverted signal version of their respective logical contents. V

25. A binary counter comprising a register having a pluralityof stages for containing signals representing in binary form the equivalent of a given decimal number; and means for changing that number by decimal one in two phase times comprising: a plurality of And circuits divided into groups respectively associated with said stages with all said groups except that associated with the first register stage having more than one of said And circuits, each of said And circuits having at most a maximum capacity of logical inputs less in number by at least two than the number of stages in said register, means including means in said register for providing during a first phase time normal and inverted signal verisons of signals in said register, a plurality of Or circuits respectively associated with said groups of And circuits with an output of each And circuit being coupled to an input of its associated Or circuit, and means for applying said normal and inverted signal versions as logical inputs simultaneously to and conditionally through said And circuits, within the limits of said maximum capacity, to said Or circuits during a second phase time to cause from the Or circuits a binary signal representation of a second decimal number which is difierent by decimal one than.

said given decimal number.

'26. A binary counter comprising a first register for at least initially containing signals representinga binary number in N binary stages each capable of providing at least one normal output of its contents with each of at least some of said stages being capable of additionally providing at least one inverted output of its contents, a slave register having N binary stages respectively asso ciated with the stages of said first register, each stageof the slave register being capable of providing normal and inverted outputs of its contents, a sensing register having N binary stages associated with the respective stages of said first and slave registers, at least some of the sensing register stages being capable of producing normal and inverted outputs of their respective contents, means for applying, during a first phase time, normal outputs of the,

first register to respective stages of said slave register, a

normal output of the first stage of said first register tothe first stage ofsaid sensing register, and inverted and normal outputs from said first register in certain combinations to the remaining sensing register stages, a predetermined number of And circuits for each counter stage, and means coupling certain inverted and normal outputs from the slave and sensing registers as respective logical inputs to and conditionally through said And circuits during a second phase time, with each such. And circuit receiving no more than (N P) of those logical inputs where P is an integer greater than one but less than N, for causing the Anding results at-each stage as a whole to represent a respective digit of a binary number whose decimal equivalent is diflerent by one than the decimal equivalent of the aforementioned binary number.

27. A counter as in claim 26 wherein said applying means includes a plurality of second And circuits for respectively and conditionally applying different groups of first register normal outputs to part of the said remaining sensing register stages and aplurality of Or circuits respectively coupled to the rest of the said remaining sensing register stages for applying thereto respectively different groups of said first register inverted outputs, each of said groups of first register normal outputs containing no more then (N P) of such outputs.

'28. A binary counter comprising a first register for at least initially containing signals representing a binary number in N binary stages each capable of providing at least one normal output of its contents with each of at least some of said stages being capable of additionally providing at least one inverted output of its contents, a slave register having N binary stages respectively associated with the stages of said first register, each stage of the slave register being capable of providing normal and inverted outputs of its contents, a sensing register having N binary stages associated with the respective stages of said first and slave registers, each of the sensing register stages being capable of producing at least one normal output with each of at least some of the sensing register stages being capable of additionally producing at least one inverted output of its contents, means for applying, during a first phase time, normal outputs of the first register to respective stages of said slave register, a normal output of the first stage of said first register to the first stage of said sensing register, and inverted and normal outputs from said first register in certain combinations to the remaining sensing register stages, a plurality of And circuits divided into groups respectively associated with the counter stages with all said groups, except that group associated with the first counter stage, having more than one of said And circuits, a plurality of Or circuits respectively associated with said groups of And circuits with an output of each And circuit being coupled to an input of its associated Or circuit, and means coupling certain inverted and normal outputs from the slave and sensing registers as respective logical inputs to and conditional through said And circuits, With each of said And circuits receiving no more than (N -P) of those logical inputs Where P is an integergreater than one but less than N, and to said Dr circuits during a second phase time for causing from the Or circuits a binary signal representation of a decimal number which is different by one than the decimal equivalent of the aforementioned binary number.

29. A counter as in claim 28 wherein said applying means includes a plurality of second And circuits for respectively and conditionally applying different groups of first register normal outputs to some of the said remaining sensing register stages and a plurality of second Or circuits respectively coupled to the rest of the said remaining sensing register stages for applying thereto respectively dilferent groups of said first register inverted outputs, each of said groups of first register outputs containing no more than (N P of such outputs.

30. A binary counter comprising means for providing signals representing normal and complemented binary digits of a binary number, a plurality of means for respectively combining different groups of said binary signals' into at least one respective logical Nor signal for each such group during a first phase time and holding said Nor signals over into a second phase time, a plurality of means for respectively combining different groups of said binary signals into at least one logical And signal for each group also during said first phase time and holding said And signals over into said second phase time, and a plurality of means operative during said second phase time to efiectively combine certain forms of all said signals into a plurality of binary signals representative of said binary number changed in value by decimal one.

References Cited by the Examiner UNITED STATES PATENTS 2,837,278 6/58 Schreiner et al. 235-l76 2,907,526 10/59 Havens 235174 2,910,240 10/59 Havens 235174 2,962,212 11/60 Schneider 235-92 3,108,226 10/63 Douglas 328-42 MALCOLM A. MORRISON, Primary Examiner.

WALTER W. BURNS, JR., Examiner. 

1. A BINARY COUNTER COMPRISING MEANS FOR AT LEAST TEMPORARILY STORING A PLURALITY OF BINARY SIGNALS REPRESENTING A BINARY NUMBER, MEANS FOR COMBING CERTAIN OF SAID SIGNALS INTO AT LEAST ONE SIGNAL REPRESENTING A LOGICAL NOR FUNCTION OF THE SO-COMBINED SIGNALS, MEANS FOR COMBINING CERTAIN OF SAID BINARY SIGNALS INTO AT LEAST ONE SIGNAL REPRESENTING A LOGICAL AND FUNCTION OF THE SO-COMBINED SIGNALS, AND MEANS FOR EFFECTIVELY COMBINING ALL OF SAID SIGNALS INTO A PLURALITY OF BINARY SIGNALS REPRESENTATIVE OF SAID BINARY NUMBER CHANGED IN VALUE BY DECIMAL ONE. 